JETSON TX1 HEADER PINOUT

Jetson TX1 J21 Header Layout. Last edited: March 12, 2018
The Jetson TX2 table is different in its GPIO numbering.

Jetson TX1 J21 Header
Sysfs GPIO Name Pin Pin Name Sysfs GPIO
3.3 VDC
Power
1
2
5.0 VDC
Power
SDA1
General I2C #0 Data 3.3.V, I2C Bus 0
3
4
5.0 VDC
Power
SCL1
General I2C #0 Data 3.3.V, I2C Bus 0
5
6
GND
gpio216 GPIO_GCLK
AUDIO_MCLK Audio Master Clock (1.8/3.3.V)
7
8
TXD0
UART #0 Transmit
GND
9
10
RXD0
UART #0 Receive
gpio162 GPIO_GEN0
UART #0 Request to Send
11
12
GPIO_GEN1
Audio I2S #0 Clock
gpio11
gpio38 GPIO_GEN2
Audio Code Interrupt
13
14
GND
gpio511 GPIO_GEN3
From GPIO Expander (P17)
15
16
GPIO_GEN4
Unused
gpio37
3.3 VDC
Power
17
18
GPIO_GEN5
Modem Wake AP GPIO
gpio184
gpio16 SPI_MOSI
SPI #1 Master Out/Slave In
19
20
GND
gpio17 SPI_MISO
SPI #1 Master In/Slave Out
21
22
GPIO_GEN6
From GPIO Epander (P16)
gpio510
gpio18 SPI_SCLK
SPI #1 Shift Clock
23
24
SPI_CE0_N
SPI #1 Chip Select #0
gpio19
GND
25
26
SPI_CE1_N
SPI #1 Chip Select #1
gpio20
ID_SDA
General I2C #1 Data (3.3V), I2C Bus 1
27
28
ID_SCL
General I2C #1 Clock (3.3V), I2C Bus 1
gpio219 GPIO5
Audio Reset (1.8/3.3V)
29
30
GND
gpio186 GPIO6
Motion Interrupt (3.3V)
31
32
GPIO12
Unused
gpio36
gpio63 GPIO13
AP Wake Bt GPIO
33
34
GND
gpio8 GPIO19
AUDIO I2S #0 Left/Right Clock
35
36
GPIO16
UART #0 Clear to Send
gpio163
gpio187 GPIO26
(3.3V)
37
38
GPIO20
Audio I2S #0 Data in
gpio9
GND
39
40
GPIO21
Audio I2S #0 Data in
gpio10
I2C Connection for Jetson TX1
NVIDIA Jetson TX1 J21 Header

Note: The arrow on the circuit board points to pin 1. Pin 2 is behind pin 1 in the picture.

I2C Bus 1 address 0x0040, 0x0042,0x0043 are the INA3221x power monitors

Notes

Here is a spreadsheet which maps the J21 signals back through the carrier board, to the module, and to the Tegra chip itself:

Google Doc Spreadsheet

Spreadsheet, .xlsx format

Helpful explanation of Pinmux, Kernel, SPI and GPIO